Why Traditional PCB Methods Fall Short in 3D IC Design

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Why Traditional PCB Methods Fall Short in 3D IC Design

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Why are companies rapidly adopting fan-out wafer-level packaging (FO-WLP)—and how does this shift impact the traditional chip design process? In this episode of the Siemens 3D IC Podcast Series, host John McMillan is joined by Chris Cone, IC Packaging Product Marketing Manager at Siemens EDA, to explore how fan-out wafer-level packaging is transforming advanced semiconductor packaging workflows. Chris shares his journey from analog design engineer to packaging and automation expert, and breaks down the growing need for intelligent, automated workflows that support the increasing complexity and size of modern designs. They discuss how new IC packaging techniques demand more automation, design iteration, and cross-functional collaboration than ever before—and why building a replayable, flexible automation language is the key to faster, scalable design success. Whether you're a layout engineer, SI/PI analyst, or replay coordinator, this episode will show you how to streamline your process using a common design framework and why human-readable automation is the next big leap in fan-out design. What You’ll Learn in this Episode: Chris Cone’s journey from analog IC designer to Siemens EDA packaging lead (1:10) What is fan-out wafer-level packaging, and why is it gaining traction? (1:50) How FOWLP is different than a traditional BGA design process (2:30) The four major phases in a fan-out packaging workflow, from tech setup to final verification (3:45) What is the impact on different roles, such as a package designer, layout designer, engineer, signal integrity, power, and integrity analysis? (8:00) The three essential traits of successful design automation (10:00) Key takeaways from real-world projects using Siemens’ automated packaging flows (11:45) Connect with John McMillan LinkedIn Website Connect with Chris Cone Website